Structure

CMOS logic uses a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gartes and other digital circuits found in computers, telecommunications and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters. These bits of silicon are commonly called chips, although within the industry they are also referred to as die (singular) or dice (plural).

In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the output and the lower-voltage power supply rail (often named V_ss or quite often ground). Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the output and the higher-voltage rail (often named V_dd). Now pull-up and pull-down refer to the idea that the output node, which happens to be where the pull-up and pull-down networks intersect, exhibit some internal capacitance that is charged or discharged respectively through pathways formed by the p/nMOS networks for various inputs. This capacitance is charged when there is a direct path from Vdd to the output, and discharged when there is a direct path from output to ground. Notice that a digital CMOS circuit cannot (ideally) be in a pull-up and pull-down phase at the same time, or else both the p/n-networks will fight to keep the voltage on the capacitance either Vdd or ground. The p-type transistor network is complementary to the n-type transistor network, so that when the n-type is off, the p-type is on, and vice-versa.

CMOS logic dissipates less power than NMOS logic because CMOS dissipates power only when switching (dynamic power). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happen once every ten nanoseconds. NMOS logic dissipates power whenever the output is low (static power), because there is a current path from V_dd to V_ss through the load resistor and the n-type network.

P-type MOSFETs are complementary to n-type because they turn on when their gate voltage goes sufficiently below their source voltage, and because they can pull the drain all the way to V_dd. Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is off, and vice-versa.